Much of the progress in making computers and memory devices faster, smaller and less expensive involves integration, squeezing ever more transistors and other electronic structures onto a postage stamp sized piece of silicon. A postage stamp sized piece of silicon may contain tens of millions of transistors, each transistor as small as a few hundred nanometers. The escalating requirements for high density and performance associated with ultra large-scale integration require responsive changes in semiconductor technology.
Semiconducting devices include, among other components, a plurality of sequentially formed dielectric interlayers and conductive patterns. Typically, the conductive patterns in two layers, such as upper and lower layers, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate. The increasing complexity of semiconducting devices demands more effective metallization methods and materials.
In recent years copper (Cu) is emerging as an alternative to aluminum (Al) for metallization patterns, particularly for interconnect systems having smaller dimensions. Some of the benefits of Cu include low resistivity, resistance to electromigration, and stress avoiding properties. Despite the beneficial properties, Cu usage in large-scale semiconductor manufacturing raises some concerns, which need to be addressed.